This application relates to power bus faults, and more specifically to a circuit operable to detect power bus faults.
Power buses deliver power from a source to a load. Electrical power buses are conductors insulated from unintended conduction paths used to convey power from a source to a load. Certain conditions, such as chafing, age, or wear, can cause power bus faults, such as undesirable connections to an unintended conductor or return path. Such faults divert power from the power bus causing the amount of power leaving the source to not be equal to the amount of power arriving at the load. A method of detecting faults, called the “Differential Power” or “DP” method, detects a difference in power between source and load and, if the difference is excessive (exceeds a threshold), indicates a fault. The subject of this application is an improved method of implementing the “Differential Power” method of bus fault detection.
The effectiveness of the “Differential Power” method of bus fault detection depends largely upon the accuracy and reliability of a circuit used to implement the method. The more accurately the circuit can determine if there is a power difference, the smaller the fault current can be that the circuit can dependably identify. The “Differential Power” method can therefore be used to detect even small faults, before they cause injury or damage. Reliability, as defined for this application, is the likelihood the circuit will falsely fail to report a bus fault due to a circuit failure.
FIG. 1 schematically illustrates a first, prior art circuit 18a for detecting a bus fault using the “Differential Power” method. The circuit is compatible with transducers 20, 22 that output signals 24, 26, 28, 30 whose current amplitude is proportional to the sensed power flowing through the power bus 16 (see FIG. 3). A current transformer (“CT”) is an example of such a transducer. Although current transformers sense current, the current in the power bus in many applications is proportional to the power in the power bus, and therefore a current transformer may be used with the “Differential Power” method. The voltage across resistor 34 is proportional to a difference in current output of the transducers 20, 22. A signal conditioner 40a conditions the voltage input signals 51, 52 to produce a conditioned difference signal 42 suitable for the control module 44 to follow. A control module 44 evaluates an amplitude of the conditioned difference signal 42, and if the amplitude is excessive (exceeds a first threshold), the control module 44 indicates a bus fault.
FIG. 2 schematically illustrates a second, prior art circuit 18b for detecting a bus fault using the “Differential Power” method. The circuit 18b is compatible with transducers 20, 22 that output signals 24, 26, 28, 30 whose current amplitude is proportional to the sensed power flowing through the power bus 16 (see FIG. 3). Signal conditioners 40b-c condition the input signals 24, 26, 28, 30 emanating from the transducers 20, 22, and produce a source current signal 46 and a load current signal 48 suitable for a control module 50 to follow. The control module 50 determines a difference between an amplitude of each of the signals 46, 48, and if the amplitude of the difference is excessive (exceeds a second threshold), the control module 50 indicates a bus fault.
A circuit's reliability is improved by the use of BITE (“Built In Test Equipment”). BITE is circuitry built into a given circuit that verifies if the circuit is still functional. Without BIT (“Built In Test”), the probability of circuit failure is calculated over the life of the product or for the duration of time between scheduled maintenance, at which time the circuitry is tested. However, the reliability of a circuit using BITE is calculated over the period of time between BIT tests, which is often very brief. Thus, the decreased time period between tests offered by BITE significantly increases reliability. A feasible, cost effective method to BIT the resistor 38 of FIG. 1 is not known within the industry. Thus, the circuitry of FIG. 2 can be made very reliable, as can much of the circuitry of FIG. 1, but not the resistor 38 of FIG. 1.
A technique often used in conjunction with BITE is to stimulate (abbreviated “STIM”) the circuit to be tested. A STIM signal injects a known signal into the circuitry to be tested. Control circuitry (or software) verifies that the circuit produces the expected output signal while it is stimulated.
The circuit 18a of FIG. 1 stimulates the signal conditioner 40a. Since the difference signal 42 output of the signal conditioner 40a is negligible during normal use while no bus faults exist, there is no way to distinguish a circuit that is failed from one that is correctly reporting no difference current, unless the circuit is stimulated. However, a feasible, cost effective method of stimulating the resistor 34 of FIG. 1 is not known.
The circuit of FIG. 2 does not require stimulation of the signal conditioners 40b-c. Because the output of the signal conditioners 40b-c are equal and non-zero during normal use, while no bus faults exist, the circuit can be verified to be working by verifying that the output values of the signal conditioners 40b-c are equal and non-zero.
However, each of the known circuits 18a, 18b has deficiencies. The circuit 18a of FIG. 1 is less reliable than the circuit 18b because if the resistor 38 of FIG. 1 fails, the circuit 18b could erroneously fail to detect a difference between the source and load current and could therefore erroneously not indicate a bus fault. Also, as discussed above, a STIM signal cannot be used to verify that the resistor 34 is functioning properly.
The circuit 18b of FIG. 2 is inherently less accurate than the circuit 18a of FIG. 1. Each circuit element introduces error, and since the circuit 18b of FIG. 2 has multiple additional signal conditioners 40b-c it can not be made as accurate as that of FIG. 1, all other conditions being equal. Also, because the signal conditioning circuit module 40a of FIG. 1 operates on the difference signal, its error affects only the difference signal, whereas the signal conditioners 40b-c of FIG. 2 operate on source signal 24, 26 and load signal 28, 30 having a larger amplitude than the difference signal of the circuit 18a. Thus, for an error contributed by a given signal conditioning circuit module to the total circuit 18b is many times larger than in FIG. 1.
For example, suppose the source current 24, 26 is 100 Amps and the load current 28, 30 is 99 Amps, resulting in a current difference of 1 Amp. Further, suppose the error of the signal conditioners 40a-c is 1% and all other circuit elements are ideal (0% error). In this example, the circuit 18a of FIG. 1 determines a voltage across resistor 34 corresponding to 1 amp and the signal conditioner 40a processes that signal with ±1% error, potentially introducing an error of 0.01 Amps (1% of 1 Amp). The circuit 18b of FIG. 2 has a ±200% error, as the signal conditioner 40b potentially introduces an error of 1 Amp (1% of 100 Amps), and the signal conditioner 40c potentially introduces an error of 1 Amp (1% of 99 Amps), yielding an overall potential error of 2 Amps (200% of 1 Amp).